Decades of increases in transistor density on integrated circuit chips have far outpaced current strategies for getting information onto and off of the chips. The need to have a secure and reliable connection under a wide variety of operating conditions, while retaining the ability to assemble chips into larger modules, has placed hard minimums on the feature sizes of the input/output (I/O) connections. Advances in manufacturing and materials continue to increase the number of transistors that can be positioned on a chip at a rate that approaches the Moore's Law curve. However, the number and size of reliable off-chip connections has nearly reached physical limits. Many prior art approaches have attempted to address this problem.
One approach is to use multiplexed data/address busses. However, with modern microprocessors commonly using 64-bit data and address busses, and some using 128, 256 or more bits, even multiplexing is unable to keep up with the growth in processing power. Furthermore, the increase in processor speed combined with the use of multiple core processors has made even the short time required to multiplex data and addresses onto the same pins a relatively long or slow operation compared to the processing ability of the chip. As such, the I/O has become the rate limiting factor or bottleneck in the system.
As component size decreased, the original ubiquitous DIP package was replaced with miniDIP, and in turn surface-mount technologies like SOP, TSOP, QFP, Pin-Grid Array (PGA), Ball-Grid Array (BGA) and others, all in the attempt to further miniaturize I/O connections and to further increase the information density across the on/off chip interfaces.
In addition to physical packaging constraints, higher frequency signals that are more densely packed present challenges related to electromagnetic interference and cross-coupling of on-chip signals. In particular, as clocking speeds increased, coupling or crosstalk between signals increased, leading to adoption of differential-pair interconnections for transferring high-speed data. While addressing the signal coupling or crosstalk issue, this approach required two I/O connections for each I/O path and therefore did not contribute significantly to increasing I/O capacity.
XAUI, an attachment unit interface standard, and other grouped differential bus standards were created to enable very high speed clocking of the I/O path. However, these standards are also reaching limits as the data transfer speeds approach 40 gigabits-per-second (GBPS) to 100 GBPS. A separate clock (typically 1.25 GHz or a multiple) synchronizes transmitters and receivers at each end of the XAUI bus. Various types of encoding, such as 8b/10b or 64b/66b encoding may be used to aid in synchronization.
As more and more systems begin to incorporate on-the-fly audio and video encoding, it is likely that even combinations of all of the best current approaches will be taxed to keep pace with the ever-increasing bandwidth demands of people, the internet, and the processors that deliver the data.
Various coding strategies have been developed to transmit information over a limited bandwidth channel. One coding strategy used extensively in radio frequency (RF) applications is referred to as Quadrature-Amplitude Modulation (QAM). In this strategy, a sine wave has both its phase and amplitude changed simultaneously to encode information. A QAM diagram has phase and amplitude (or Q and I) axes, with designated “allowable” locations or values (also referred to as stations) for phase/amplitude combinations that define a QAM constellation. The QAM strategy may be referred to by an integer that corresponds to the number of stations in the constellation. As such, a QAM strategy having an arbitrary number “N” of stations in its constellation may be generally referred to as “nQAM”.
For example, a typical nQAM with N=16 stations in its constellation (16QAM) may be represented as illustrated in FIG. 1. The vertical axis represents the “Q” (Quadrature or Phase) value of the modulated sine wave while the horizontal axis represents the “I” (In-phase or Amplitude) value. Each station, generally represented by station 20, within the constellation 30 is assigned a value that represents the bits 32 transmitted when that station is visited. In the example illustrated in FIG. 1, each station 20 represents four (4) bits from 0000 to 1111. While a particular pattern of bits 32 may be assigned to any station 20, the stations are typically arranged and numbered using a GRAY code such that only single-bit-changes occur between adjacent stations. For example, station 24 has an associated bit pattern 34 of “0101”. Adjacent station 26 has an associated bit pattern 36 of “0100” that differs from bit pattern 34 by a single bit. Similarly, adjacent station 28 has an associated bit pattern 38 of “0001” that differs from bit pattern 34 by a single bit.
Conventional implementations of a QAM coding strategy to transfer data use a base sine wave with one or more devices to provide near-instantaneous modification of the phase and/or amplitude of the sine wave to transition from one constellation station to another. One technique generates phase-locked sine and cosine waves, using the Q value to modulate the amplitude of the cosine wave, and the I value to modulate the amplitude of the sine wave. The two waves are then combined using a mixer to create the transmitted RF output. The channel bandwidth required for transmitting the data is determined by the symbol rate and Nyquist's theorem.
Multiple simultaneous streams of information can be transferred using wideband transmitters/receivers in combination with multiple center-carrier sine waves of different frequencies, separated by at least the bandwidth of each individual information stream.
Recent increases in demand for internet bandwidth-to-the-home have taxed the limits of earlier modulation techniques over the ubiquitous twisted-pair copper wires used for POTS (Plain Old Telephone Service) delivery. The International Telecommunications Union (ITU) has responded to this rapid ramp-up in bandwidth demand by promulgating standards that continue to evolve. Beginning with DSL, the standards that provide additional bandwidth delivery include VDSL (G993.1) and VDSL2 (G993.2). These standards use RF over twisted-pair copper wires in combination with coding techniques such as QAM to create multiple subscriber bands over a single twisted pair.
While such standards are being used to address the bandwidth demands of multi-drop lines from a central office or headend servicing various subscribers, they are overly complex and not currently practical for typical digital systems where most of the information is transferred point-to-point with fan-out handled by dedicated nodes rather than multi-drop lines (e.g. single card, or backplane-interconnected cards, or wire-and-hub networking). At very high speeds, the stubs associated with multiple listeners become difficult to manage, and line reflections, in-coupled noise, and other issues quickly drive high-speed data systems to full-mesh point-to-point designs. Furthermore, attempting to reduce the size of the required encoders, transmitters, receivers, and decoders for VDSL and/or VDSL2 systems so that they could be used as generic chip-to-chip interfaces is beyond problematic.
Digital systems are prone to significant spectral emissions, especially as processor and data rates have continued to increase. To significantly reduce emissions, many modern designs use differential pair signaling and run the differential pairs for XAUIs and other high speed connections on interior layers of a chip or card sandwiched between ground and/or voltage planes to guarantee low radiated emissions from the high speed lines. Radiated emissions are generated in response to switching transients. For example, as a bit on a CMOS integrated circuit changes state from 0 to 1 or from 1 to 0, the nature of the circuit design results in a brief moment when there is a relatively high current flow from power to ground, resulting in a current (and emissions) spike. The switching periods also account for the bulk of the power consumed in CMOS integrated circuits. This is true even for differential pairs, where the two wires are switched to opposite states. During the transition, there are high voltage and current transients in both wires. With perfect switching these transients would be exactly in synch and of opposite sign and would still cancel in the far field. Unfortunately, switching is rarely perfect so switching transients radiate even from well-matched differential pairs.
As such, the present disclosure recognizes a need for increasing the capacity of existing integrated circuit I/O without consuming significant on-chip resources or power budgets, and without a significant increase in radiated emissions.
In addition, the present disclosure recognizes that storage of information requires storing and recovery of the voltage/current used for transmitting this information, and that the most space-efficient mechanisms use a single capacitor to store a bit as a voltage.